A typical write circuit generates a square wave current pattern through the write head, with each current pulse being composed of a rise time portion, an overshoot portion, and a steady state portion. The overshoot portion represents the portion of the pulse where the absolute value of the current exceeds the absolute value of the steady state current. For example, where the steady state current is 40 mA, the overshoot current may reach a peak of 125 mA. The rise time is generally defined as the time that it takes the current to change from 10% to 90% of its steady state current, as it swings from one direction to the other. Thus, for a write head driver programmed to generate a 40 mA steady state write current, the rise time is defined as the time required for the current in the write head to change from −32 mA to +32 mA, and vice versa.
There have been many improvements to conventional write circuits to enhance their performance. These improved current-switching write circuits, however, are still unable to achieve impedance matching to the interconnect, since such impedance matching would require a small resistor in parallel with the write head which would shunt the write current away from the write head during operation of the circuit and thereby render the circuit inoperable. The lack of impedance matching results in pattern dependent distortion which limits the performance of the write circuit.
A number of techniques have been proposed or suggested to ensure impedance matching between the write circuit and the interconnect, in order to reduce pattern dependent distortion. U.S. Pat. No. 6,512,646 to Leighton et al., incorporated by reference herein, discloses an impedance matched write circuit that employs current sources that supply current during an overshoot mode that does not go through the matching resistor. U.S. Pat. No. 6,121,800 to Leighton et al., incorporated by reference herein, discloses an impedance matched write driver circuit in which a voltage-mode writer is arranged in parallel with an impedance-matched writer to ensure that the maximum available voltage is delivered to the head pins.
When impedance matched writers go into an overshoot mode, as much current and voltage as possible should be launched into the interconnect. For series terminated matched writers, this incurs a voltage drop penalty across the matching resistor. However, during the overshoot duration, matching is not necessary. A need therefore exists for a matching resistor in a write head that can be shunted to reduce the voltage drop across the matching resistor and deliver more voltage launch to the interconnect.